Methods and systems for inspection of wafers and reticles using designer intent data

ABSTRACT

Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the wafer in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.

PRIORITY CLAIM

This application claims priority to U.S. Provisional Application No.60/485,338 entitled “Methods and Systems for Inspection of Wafers andReticles Using Designer Intent Data,” filed Jul. 3, 2003, which isincorporated by reference as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to methods and systems forinspection of wafers and reticles using designer intent data. Certainembodiments relate to systems and methods for detecting defects on awafer based on data representative of a reticle or data produced byinspection of a reticle.

2. Description of the Related Art

Fabricating semiconductor devices such as logic and memory devicestypically includes processing a specimen such as a semiconductor waferusing a number of semiconductor fabrication processes to form variousfeatures and multiple levels of the semiconductor devices. For example,lithography is a semiconductor fabrication process that typicallyinvolves transferring a pattern to a resist arranged on a semiconductorwafer. Additional examples of semiconductor fabrication processesinclude, but are not limited to, chemical-mechanical polishing, etch,deposition, and ion implantation. Multiple semiconductor devices may befabricated in an arrangement on a semiconductor wafer and then separatedinto individual semiconductor devices.

During each semiconductor fabrication process, defects such asparticulate contamination and pattern defects may be introduced intosemiconductor devices. Such defects may be found either randomly on aspecimen surface or may be repeated within each device formed on aspecimen. For example, random defects may be caused by events such as anunexpected increase in particulate contamination in a manufacturingenvironment and an unexpected increase in contamination in processchemicals that may be used in fabrication of a semiconductor device.

Defects may also be formed in a systematic fashion over time and due toindividual process marginalities and interactions of multiple processes.Defects caused by individual process marginalities or by interactionsbetween multiple processes may result in defects such as a filmthickness variation or a lateral dimension variation due to dosevariation. Such defects may, in turn, result in a defect in asemiconductor device formed on the specimen such as bridging between twoconductive structures thereby forming a short between the structures.Defects repeated within each semiconductor device formed on an entirespecimen may, for example, be systematically caused by contamination ordefects found on a reticle, or a mask. Contamination or defects on areticle may be transferred along with a device pattern to a resistduring a lithography process.

As the dimensions of advanced semiconductor devices continue to shrink,the presence of defects in the semiconductor devices limits thesuccessful fabrication, or yield, of a semiconductor device. Forexample, a reticle defect reproduced in a resist patterned duringlithography may cause an open circuit or a short circuit in asemiconductor device formed in subsequent processing. Becausefabrication of a semiconductor device includes many complex processsteps, the adverse effects of defects on total yield may increaseexponentially if an error that is caused by a defect is propagatedthroughout an entire manufacturing process or operation over time.

SUMMARY OF THE INVENTION

An embodiment of the invention relates to a computer-implemented methodthat includes identifying nuisance defects on a wafer based oninspection data produced by inspection of a reticle. The reticle is usedto form a pattern on the wafer prior to inspection of the wafer. Thenuisance defects may be formed on the wafer as a result of defects onthe reticle that were determined to be permissible reticle defects. Inone embodiment, the nuisance defects may be formed on the wafer as aresult of defects on the reticle that were determined to be permissiblereticle defects based on designer intent data. In further embodiments,if the nuisance defects are formed on the wafer as a result of defectson the reticle that were determined to be permissible reticle defects,the method may include analyzing the nuisance defects to determine ifthe permissible reticle defects were correctly classified. In someembodiments, if the permissible reticle defects were not correctlyclassified, the method may include determining if the reticle should beanalyzed, reworked, or disposed. In another embodiment, the method mayinclude determining if the nuisance defects will affect yield ofsemiconductor devices, which will be formed on the wafer.

In some embodiments, the method may include separating the nuisancedefects from actual defects on the wafer. Such embodiments may alsoinclude processing data representative of the actual defects, but notthe nuisance defects. In additional embodiments, the method may includegenerating a two-dimensional map of the wafer. The nuisance defects maybe distinguished from other defects in the map by one or more differentdesignations.

In another embodiment, the method may include transmitting theinspection data from an inspection system used to perform the inspectionof the reticle to a processor configured to perform the method. In adifferent embodiment, the method may include transmitting the inspectiondata from a fab database to a processor configured to perform thecomputer-implemented method. In one such embodiment, transmitting theinspection data may include sending coordinates of defects detected onthe reticle and images of the defects. In an additional embodiment, ifthe inspection data includes coordinates of a location of a defect onthe reticle, the method may include translating the coordinates of thelocation of the defect to coordinates of locations of one or more of thenuisance defects on the wafer. The method may include any other steps ofany of the methods described herein.

An additional embodiment relates to a computer-implemented method thatincludes identifying locations on a wafer in which nuisance defects willbe formed based on inspection data produced by inspection of a reticle.In one embodiment, the method may also include selecting one or moreparameters for wafer inspection such that the locations of the nuisancedefects are not inspected. In a different embodiment, the method mayinclude selecting one or more parameters for wafer defect review suchthat the nuisance defects are not reviewed. In another embodiment, themethod may include selecting one or more parameters for wafer defectanalysis such that the nuisance defects are not analyzed.

Another embodiment relates to a computer-implemented method thatincludes identifying critical portions of a wafer based on thecriticality associated with different areas of the wafer. The methodalso includes selecting parameters for inspection of the wafer such thatonly the critical portions of the wafer are inspected. In someembodiments, the parameters may be selected such that nuisance defectson the wafer are not classified as actual defects. In one embodiment,the parameters may be selected such that critical portions of the waferhaving different criticalities are inspected with different parameters.According to another embodiment, the method may include setting one ormore parameters for classification of defects on the wafer based on thecriticality of the critical portions.

In another embodiment, the method may include assigning a designation toa defect on the wafer based on the criticality of the critical portionin which the defect is located. In a different embodiment, the methodmay include determining processing of a defect on the wafer based on thecriticality of the critical portion in which the defect is located. Insome embodiments, the method may include classifying defects on thewafer as critical defects or non-critical defects and analyzing aprocess performed on the wafer based on the critical defects and thenon-critical defects. In another embodiment, the method may includeclassifying defects on the wafer as critical defects or non-criticaldefects and processing the critical defects separately from thenon-critical defects.

According to an additional embodiment, the method may include discardinginspection data representing defects in one of the critical portions ifthe defects have a lateral dimension smaller than a predeterminedthreshold and if other features in the one portion have a lateraldimension greater than the predetermined threshold. In a differentembodiment, the method may include discarding inspection datarepresenting defects in one of the critical portions if an element of acircuit in the one portion has a predetermined amount of redundancy andif the defects in the one portion do not exceed a predetermined densitythreshold.

In some embodiments, the method may include translating coordinates of alocation of a defect detected on a reticle to coordinates of locationsof one or more defects on the wafer. Such an embodiment may also includeanalyzing the printability of the defect detected on the reticle. Inanother such embodiment, the method may include removing inspection dataat the coordinates on the wafer from the wafer inspection data.

In one embodiment, the method may include generating one or moretwo-dimensional maps illustrating the critical portions of the wafer.The inspection may be performed on one level of the wafer. In oneembodiment, the method may include identifying the criticality of adefect on the wafer based on the criticality of the critical portion inwhich the defect is located and data representative of at least onelayer of the wafer above or below the one level. In another embodiment,the method may include generating a three-dimensional representation ofthe defect, the one level, and at least the one layer of the wafer aboveor below the one level.

A further embodiment relates to a computer-implemented method thatincludes determining one or more parameters for wafer defect reviewbased on the criticality associated with different areas of the wafer.In one embodiment, the method may include selecting the one or moreparameters such that only defects located in critical portions of thewafer are reviewed. In one such embodiment the one or more parametersmay be different for one or more of the critical portions. In anotherembodiment, the method may include sending information about thecriticality of the different areas of the wafer to a tool configured toperform the wafer defect review.

Another embodiment relates to a computer-implemented method thatincludes determining one or more parameters for wafer defect analysisbased on the criticality associated with different areas on the wafer.The method may include selecting the one or more parameters such thatonly defects located in critical portions of the wafer are analyzed insome embodiments. In such an embodiment, the one or more parameters maybe different for one or more of the critical portions. In otherembodiments, the method may include sending information about thecriticality of the different areas of the wafer to a tool configured toperform the wafer defect analysis.

An additional embodiment relates to a computer-implemented method thatincludes identifying bad die on a wafer. In an embodiment, identifyingthe bad die may include performing functional testing on the wafer aftera manufacturing process used to process the wafer is completed. The baddie may contain one or more electrical elements having functionalityoutside of a predetermined range. The method also includes identifying afirst portion of defects and a second portion of defects on the waferbased on data generated by inspection of the wafer in combination withinformation representative of a design of the one or more electricalelements. In one embodiment, the data generated by inspection of thewafer may include data generated by multiple inspections of the wafer,which may be performed at different times during the manufacturingprocess. The first portion of the defects may alter a characteristic ofa device formed by the one or more electrical elements such that thecharacteristic is outside of the predetermined limits. In addition, themethod may include determining a property of the manufacturing processbased on the first portion of the defects. In one embodiment, theproperty may be a kill ratio of the first portion of the defects. In adifferent embodiment, the property may be a yield of the manufacturingprocess. In some embodiments, the method may include altering one ormore parameters of the manufacturing process based on the property. Themethod may further include any other steps of any of the methodsdescribed herein.

A further embodiment relates to a computer-implemented method thatincludes altering a design of an integrated circuit (IC) based on datagenerated by inspection of a wafer during a manufacturing process. Thedata generated by inspection of the wafer includes information aboutdefects detected on the wafer, and a substantial portion of the defectsincludes critical defects that can alter one or more characteristics ofthe IC. For example, the method may include distinguishing between thecritical defects and other noncritical defects detected during theinspection based on the design. The non-critical defects are defectsthat will not substantially alter the one or more characteristics of theIC.

In one embodiment, altering the design may be performed using a feedbackcontrol technique. In another embodiment, altering the design mayinclude altering the design of the IC to reduce a number of the criticaldefects that are formed during the manufacturing process. In anadditional embodiment, the method may include identifying individualprocesses of the manufacturing process that result in at least some ofthe critical defects being formed on the wafer. In one such embodiment,the method may also include determining if the design of the ICcontributes to the formation of the critical defects. Such embodimentsmay also include altering the design of the IC to reduce the number ofthe critical defects that are formed during the individual processes. Inanother embodiment, the method may include determining a yield of themanufacturing process based on the critical defects. Such an embodimentmay also include altering the design of the IC to increase the yield ofthe manufacturing process. Yet another embodiment may include alteringthe manufacturing process based on the data. The method may furtherinclude any other steps of any of the methods described herein.

An additional embodiment relates to a storage medium. The storage mediumincludes data representative of an IC design. The storage medium alsoincludes data representative of an IC manufacturing process. Inaddition, the storage medium includes defect data representative ofdefects detected on a wafer during the IC manufacturing process. Thedefect data may be filtered such that a substantial portion of thedefects includes critical defects that can alter one or morecharacteristics of the IC. The storage medium can be used to alter theIC design based on the data representative of the IC design, the datarepresentative of the IC manufacturing process, and the defect data. Inone embodiment, the storage medium may also include data representativeof relationships between the critical defects and the IC design. Thestorage medium may be further configured as described herein.

Another embodiment relates to a computer-implemented method thatincludes simulating one or more characteristics of an IC based on datagenerated by inspection of a wafer during a manufacturing process. Inone embodiment, the one or more characteristics include, but are notlimited to, voltage drops, timing slowdowns, partial device failure, andtotal device failure. The data may include information about defectsdetected on the wafer. In an embodiment, the information about thedefects may include coordinates of defect locations andthree-dimensional defect profiles. A substantial portion of the defectsinclude critical defects that can alter the one or more characteristicsof the IC. In one embodiment, the method may also include distinguishingbetween the critical defects and other non-critical defects detectedduring the inspection based on the design. The non-critical defects willnot substantially alter the one or more characteristics of the IC. Themethod may further include any other steps of any of the methodsdescribed herein.

An additional embodiment relates to a computer-implemented method thatincludes determining placement of a pattern on a specimen based on datagenerated by inspection of the specimen. In some embodiments,determining the placement of the pattern may include laterallytranslating the pattern, rotating the pattern, scaling the pattern, orany combination thereof. In an embodiment, the specimen may be a blankreticle substrate. In a different embodiment, the specimen may be awafer. In some embodiments, determining the placement of the pattern mayinclude selecting the placement of the pattern such that a substantialportion of defects on the specimen does not overlap with the pattern. Inanother embodiment, the method may include identifying critical portionsof the pattern based on design information. In such an embodiment,determining placement of the pattern may include determining theplacement of the critical portions of the pattern with respect tolocations of defects on the specimen. In yet another embodiment,determining placement of the pattern may include selecting the placementof the pattern such that a substantial portion of defects on thespecimen does not overlap with critical portions of the pattern. In adifferent embodiment, determining placement of the pattern may includeselecting the placement of the pattern such that an amount of overlapbetween defects on the specimen and critical portions of the pattern isbelow a predetermined threshold.

In another embodiment, if the specimen is a reticle, the method mayinclude determining an amount of overlap between defects on the reticleand critical portions of the pattern. Such an embodiment may alsoinclude estimating the number of critical defects that would be producedon a wafer that is exposed with the reticle. In a further embodiment, ifthe specimen is a reticle, the method may include determining alignmentof the reticle with an exposure tool or a wafer based on the placementof the pattern with respect to a coordinate system. The method mayfurther include any other steps of any of the methods described herein.

Another embodiment relates to a computer-implemented method thatincludes determining a design significance of a defect detected on areticle. The design significance may be a measure of how the defectimpacts a design of the reticle. The method may also include determininga lithographic significance of the defect. The lithographic significancemay be a measure of how the defect impacts a wafer patterned by alithography process that uses the reticle. In addition, the method mayinclude determining an overall significance of the defect based on thedesign significance and the lithographic significance. The overallsignificance may be selected from the group consisting oflithographically and design significant, lithographically significantonly, design significant only, and not significant.

In an embodiment, the method may include determining a designsignificance of different regions on the reticle. In such an embodiment,determining the design significance of the defect may be based on thedesign significance of the region on the reticle in which the defect islocated. In another embodiment, determining the design significance mayinclude comparing data representative of the defect to a threshold anddetermining that the defect has design significance if the data isgreater than the threshold. In some embodiments, the threshold may varydepending on a location of the defect on the reticle.

In one embodiment, the method may include determining a lithographicsignificance of different regions on the reticle. In one suchembodiment, determining the lithographic significance of the defect maybe based on the lithographic significance of the region on the reticlein which the defect is located. In an additional embodiment, determiningthe lithographic significance of a defect may include comparing datarepresentative of the defect to a threshold and determining that thedefect has lithographic significance if the data is greater than thethreshold. In some embodiments, the threshold may vary depending on alocation of the defect on the reticle.

In another embodiment, the method may include determining an overallsignificance of different regions on the reticle. In one suchembodiment, the method may include determining one or more parameters ofa process used to fabricate the different regions of the reticle basedon the overall significance of the different regions. In a differentsuch embodiment, the method may include altering one or more parametersof a process used to inspect the different regions of the reticle basedon the overall significance of the different regions. In yet anothersuch embodiment, the method may include altering one or more parametersof a process used to repair the reticle based on the overallsignificance of the different regions. In this manner, a process used tofabricate, inspect, or repair a reticle may have one or more parametersin one of the different regions that are different than the one or moreparameters of the process in another of the different regions.

In some embodiments, the method may include determining one or moreparameters of a process that is used to repair the defect based on theoverall significance of the defect. The one or more parameters used torepair different defects on the reticle may be different. In anotherembodiment, the method may include determining processing of the reticlebased on the overall significance of the defect. The processing mayinclude rejecting the reticle, repairing the reticle, or cleaning thereticle.

In an additional embodiment, the method may include generating a visualrepresentation of the defect. The visual representation may include oneor more designations assigned to the defect indicating the overallsignificance of the defect. In a different embodiment, the method mayinclude generating a visual representation of individual regions on theretile. Such a visual representation may include designations assignedto the individual regions indicating the overall significance of theindividual regions. The method may further include any other steps ofany of the methods described herein.

Further embodiments relate to a carrier medium that includes programinstructions executable on a computer system to perform any of thecomputer-implemented methods described herein. Additional embodimentsrelate to a system configured to perform any of the computer-implementedmethods described herein. For example, the system may include aprocessor configured to execute program instructions for performing oneor more of the computer-implemented methods described herein. In oneembodiment, the system may be a stand-alone system. In anotherembodiment, the system may be a part of or coupled to an inspectionsystem. In a different embodiment, the system may be a part of orcoupled to a defect review system. In yet another embodiment, the systemmay be coupled to a fab database. For example, the system may be coupledto an inspection system, a review system, or a fab database by atransmission medium such as a wire, a cable, a wireless transmissionpath, and/or a network. The transmission medium may include “wired” and“wireless” portions.

BRIEF DESCRIPTION OF THE DRAWINGS

Further advantages of the present invention may become apparent to thoseskilled in the art with the benefit of the following detaileddescription of the preferred embodiments and upon reference to theaccompanying drawings in which:

FIG. 1 is a flow chart illustrating an embodiment of acomputer-implemented method that includes identifying nuisance defectson a wafer based on reticle inspection data;

FIG. 2 is a schematic diagram illustrating an inspection system coupledto a processor, which is coupled to a fab database and/or a processorconfigured to perform a computer-implemented method described herein;

FIGS. 3 a-3 d are schematic diagrams illustrating one example of howindividual layer data for an integrated circuit (IC) can be manipulatedto identify “don't care areas” on a wafer;

FIG. 4 is a flow chart illustrating an embodiment of acomputer-implemented method that includes detecting defects on a waferby analyzing wafer inspection data in combination with reticle data;

FIG. 5 is a flow chart illustrating an embodiment of acomputer-implemented method for selectively using defect information toanalyze manufacturing processes;

FIG. 6 is a flow chart illustrating an embodiment of acomputer-implemented method for altering a design of an IC based on aselected portion of defects detected on a wafer;

FIG. 7 is a schematic diagram illustrating an embodiment of a storagemedium that can be used to alter an IC design to enhance themanufacturability of the IC design;

FIG. 8 is a flow chart illustrating an embodiment of acomputer-implemented method for simulating one or more characteristicsof an IC based on defect data;

FIG. 9 is a flow chart illustrating an embodiment of acomputer-implemented method that includes determining placement of apattern on a specimen based on defect data;

FIG. 10 is a flow chart illustrating an embodiment of acomputer-implemented method for determining the significance of adefect; and

FIG. 11 is a conceptual diagram illustrating how defects on a reticlemay fall into categories of differing significance.

While the invention is susceptible to various modifications andalternative forms, specific embodiments thereof are shown by way ofexample in the drawings and may herein be described in detail. Thedrawings may not be to scale. It should be understood, however, that thedrawings and detailed description thereto are not intended to limit theinvention to the particular form disclosed, but on the contrary, theintention is to cover all modifications, equivalents and alternativesfalling within the spirit and scope of the present invention as definedby the appended claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The term “wafer” generally refers to substrates formed of asemiconductor or non-semiconductor material. Examples of such asemiconductor or non-semiconductor material include, but are not limitedto, monocrystalline silicon, gallium arsenide, and indium phosphide.Such substrates may be commonly found and/or processed in semiconductorfabrication facilities.

A wafer may include only the substrate such as a virgin wafer.Alternatively, a wafer may include one or more layers that may be formedupon a substrate. For example, such layers may include, but are notlimited to, a resist, a dielectric material, and a conductive material.A resist may include a resist that may be patterned by an opticallithography technique, an e-beam lithography technique, or an X-raylithography technique. Examples of a dielectric material may include,but are not limited to, silicon dioxide, silicon nitride, siliconoxynitride, and titanium nitride. Additional examples of a dielectricmaterial include “low-k” dielectric materials such as Black Diamond™which is commercially available from Applied Materials, Inc., SantaClara, Calif., and CORAL™ commercially available from Novellus Systems,Inc., San Jose, Calif., “ultra-low k” dielectric materials such as“xerogels,” and “high-k” dielectric materials such as tantalumpentoxide. In addition, examples of a conductive material may include,but are not limited to, aluminum, polysilicon, and copper.

One or more layers formed on a wafer may be patterned or unpatterned.For example, a wafer may include a plurality of dies having repeatablepattern features. Formation and processing of such layers of materialmay ultimately result in completed semiconductor devices. As such, awafer may include a substrate on which not all layers of a completesemiconductor device have been formed or a substrate on which all layersof a complete semiconductor device have been formed.

A “reticle” or a “mask” is generally defined as a substantiallytransparent substrate having substantially opaque regions and/orpartially opaque regions formed thereon and configured in a pattern. Thesubstrate may include, for example, a glass material such as quartz. Areticle may be disposed above a resist-covered wafer during an exposurestep of a lithography process such that the pattern on the reticle maybe transferred to the resist. For example, substantially opaque regionsof the reticle may protect underlying regions of the resist fromexposure to an energy source.

As used herein, the term “designer intent data” is used interchangeablywith the term “design information.” In addition, although someembodiments are described herein with respect to an integrated circuit,it is to be understood that these embodiments may be similarly appliedto other semiconductor devices such as microelectromechanical (MEMS)devices and the like. In addition, the term “integrated circuit” is usedinterchangeably herein with the term “semiconductor device.”

Turning now to the drawings, it is noted that the steps shown in each ofthe figures are not essential to practice of the respective methods. Oneor more steps may be omitted from or added to any of the methodsillustrated in each of the figures, and the methods can still bepracticed within the scope of these embodiments. FIG. 1 is a flow chartillustrating a computer-implemented method that includes identifyingnuisance defects on a wafer based on inspection data produced byinspection of a reticle. The method illustrated in FIG. 1 provides animproved method of wafer inspection, wafer defect classification, waferdefect review, and wafer defect analysis by utilizing designer intentdata.

As shown in FIG. 1, the method may include obtaining inspection dataproduced by inspection of a reticle, as shown in step 10. Obtaining theinspection data may include inspecting the reticle. In some embodiments,obtaining the inspection data may include receiving the inspection datafrom an inspection system used to inspect the reticle. In otherembodiments, obtaining the inspection data may include receiving theinspection data from a fab database. A fab database may includeinformation related to any of the processes performed in a fab such astool history, wafer history, and reticle history. A fab database mayalso include any set of data suitable for use in an overall fabmanagement system. An example of such a system is illustrated in PCTPublication No. WO 99/59200 to Larney et al., which is incorporated byreference as if fully set forth herein. The data may be processed by aprocessor coupled to the inspection system prior to being sent to aprocessor configured to perform the method or to the fab database. Inaddition, or alternatively, the data may be processed after beingreceived by the processor configured to perform the method.

As shown in the schematic diagram of FIG. 2, for example, inspectionsystem 12 may be used to inspect a reticle. In this manner, theinspection system will generate inspection data during inspection of areticle. The individual components of inspection system 12 shown in FIG.2 are known in the art and thus will not be described further herein.Although one configuration of a reticle inspection system is shown inFIG. 2, the inspection system may include any reticle inspection systemknown in the art. Examples of appropriate inspection systems include theSL3UV system and the TeraStar system available from KLA-Tencor, SanJose, Calif. In addition, the inspection system may be an aerial imagingbased reticle inspection system. The inspection data may be received byprocessor 14, which is coupled to the inspection system. In someembodiments, processor 14 may be incorporated into the inspectionsystem. The data may then be transmitted from processor 14 to processor16, which is configured to perform the method. In some embodiments,processor 16 may be an image computer. In addition, processor 16 mayinclude any suitable processor known in the art. In a differentembodiment, the inspection data may be transmitted from processor 14 tofab database 18. The data may then be transmitted from the fab databaseto processor 16. In any of the above embodiments, the data may betransmitted as files having a common data structure (such as KLARFF,which is commercially available from KLA-Tencor) that may be used orinterpreted by both of the processors.

Inspection system 12, processors 14 and 16, and fab database 18 may becoupled, as shown in FIG. 2, by transmission media such as wires,cables, wireless transmission paths, and/or a network. The transmissionmedia may include “wired” and “wireless” portions. In some embodiments,processor 16 may be incorporated into a wafer inspection system (notshown). In other embodiments, processor 16 may be a stand-aloneprocessor. In either embodiment, processor 16 may be coupled to a waferinspection system such that the processor may receive data generated byinspection of wafers. In other embodiments, processor 16 may receivewafer inspection data from fab database 18. In some embodiments, thedata which is transmitted to processor 16 may include coordinates ofdefects detected on the reticle and images of the defects.

Traditionally, integrated circuit (IC) design and IC manufacturing havebeen markedly separate activities with minimal overlap. However, today'sstate of the art manufacturing technology requires substantialinteraction between these two activities. The place where most of thiscollaboration takes place is at the TCAD layout phase, where theschematics from IC designers are physically placed and routed. Thiscollaboration, which is commonly referred to as “Design forManufacturability” (DFM), has raised numerous problems for waferinspection. The methods described herein, however, address many of theseproblems.

For example, as shown in FIG. 1, inspection data 10 produced byinspection of a reticle may be used in combination with designer intentdata 20 to determine permissible defects on the reticle, as shown instep 22. The designer intent data may include designations identifyingdifferent types of regions of the reticle, different types of featureson the reticle, and/or different portions of features on the reticle.The different types of regions, features, or portions of features mayinclude, for example, critical and noncritical regions, features, orportions of features as described in more detail herein. Thedesignations may vary depending upon a circuit pattern databasegenerated from an IC design. The IC design may be developed using anymethod or system known in the art such as electronic design automation(EDA), computer aided design (CAD), and other IC design software. Suchmethods and systems may be used to generate the circuit pattern databasefrom the IC design. The circuit pattern database includes datarepresenting a plurality of layouts for various layers of the IC.Therefore, data in the circuit pattern database may be used to determinelayouts for a plurality of reticles. A layout of a reticle generallyincludes a plurality of polygons that define features in a pattern onthe reticle. Each reticle is used to fabricate one of the various layersof the IC. The layers of the IC may include, for example, a junctionpattern in a semiconductor substrate, a gate dielectric pattern, a gateelectrode pattern, a contact pattern in an interlevel dielectric, and aninterconnect pattern on a metallization layer.

A circuit pattern database may include designations as described above.The designations may include, for example, flags or tags associated withdifferent types of regions, features, or portions of features on thereticle. The designations, however, may include any indicia suitable todistinguish one type of region, feature, or portion of a feature fromanother type. Each region, feature, or portion of a feature, or onlysome of the regions, features, or portions of features, on the reticlemay be associated with a designation. Data in the circuit patterndatabase representing a layout of a reticle may be separate from data inthe circuit pattern database representing the designations. In addition,different types of designations may be separated in the circuit patterndatabase. For example, the circuit pattern database may include a firstset of data that includes designations for critical regions, features,or portions of features on the reticle and a second set of data thatincludes designations for noncritical regions, features, or portions offeatures on the reticle. Alternatively, different designations may becombined into a single set of data. Data representing a layout of areticle and designations may have any form readable by a processorcoupled to an inspection system or another processor. For example, thedata may include files or other readable data including one or morefeatures and spatial positions within the reticle associated with thefeatures. Each feature may also include one or more polygons or othershapes as described herein, and a spatial position within the reticlemay also be associated with each of the polygons or shapes. Therefore,the data can be used to fabricate a reticle.

Additional examples of designer intent data and methods of use forreticle inspection are illustrated in U.S. Pat. No. 6,529,621 to Glasseret al. and PCT Application No. WO 00/36525 by Glasser et al., which areincorporated by reference as if fully set forth herein. A system ormethod as described herein may also include any of the elements or stepsillustrated by Glasser et al. The designer intent data may be provideddirectly to a processor of a wafer inspection system, a defect reviewtool, and/or a defect analysis station. In one example, the designerintent data may be sent directly to the processor of the waferinspector, the defect review tool, and/or the defect analysis stationvia a transmission medium such as that described above. One example ofan analysis station is the Klarity defects product, which iscommercially available from KLA-Tencor. The Klarity defects productprovides offline analysis of data that is taken from a wafer inspector.

Some reticles include phase shift or optical proximity correction (OPC)features. In one embodiment, the method may include simulating theprintability of such a reticle on a wafer, The simulation may beperformed using a simulation program such as PROLITH, which is availablefrom KLA-Tencor, or any other suitable simulation program known in theart. The simulation may be based on data representative of the reticleand/or data generated by inspection of the reticle. In addition, themethod may include distinguishing between critical defects andnon-critical defects on the reticle based on the simulation results anddesigner intent data. In another embodiment the method may includeremoving the phase shift or OPC features from the data representative ofthe reticle. The phase shift or OPC features may be removed using asimulation program such as PROLITH. Designer intent data may then beused to identify non-critical defects on the reticle and to optionallyfilter out non-critical defects on the reticle. Removing phase shift orOPC features from the reticle data may simplify distinguishing betweencritical defects and non-critical defects on the reticle.

Permissible defects may be identified as defects on the reticle that arelocated in non-critical portions of the reticle. In some instances,permissible defects may be identified as defects that are locatedproximate a non-critical feature on the reticle such as a teststructure. In addition, permissible reticle defects may be identified asdefects that have lateral dimensions that are smaller than apredetermined range of lateral dimensions or a predetermined thresholdfor the lateral dimensions. Alternatively, permissible reticle defectsmay be identified as reticle defects that do not alter a characteristicof the reticle such as phase and transmission such that thecharacteristic is outside of a predetermined range for thecharacteristic. In other instances, permissible reticle defects may beidentified as defects that will not print on a wafer exposed with thereticle. Alternatively, permissible reticle defects may be identified asdefects on the reticle that will not alter a pattern that is printed ona wafer exposed with the reticle such that the pattern will not have oneor more characteristics that are outside of a predetermined range forthe characteristics. For example, a permissible defect may be a reticledefect that may alter a lateral dimension of a feature printed on awafer, but does not alter the lateral dimension such that it is outsideof an acceptable range of lateral dimensions.

In general, permissible reticle defects may be any defect found on areticle that will not alter a characteristic of a reticle, a criticalportion of a reticle, a pattern on a wafer, or a critical portion of awafer such that the characteristic is outside of a predetermined rangefor the characteristic. In this manner, permissible defects on a reticlemay not be repaired prior to releasing the reticle for fabrication.Tolerating permissible reticle defects will result in such defects beingrepeatedly printed on wafers. Therefore, the permissible reticle defectsmay alter a pattern printed on a wafer with the reticle such that theprinted pattern deviates from the “ideal” pattern. As such, changes inthe pattern on the printed wafer caused by permissible reticle defectsmay be identified as defects on the wafer during inspection of thewafer. Wafer inspection systems will flag these defects (since they willgenerally show up as differences in array or random detection modes). Atthe same time, there may be other repeating defects on the wafer thatwill be interesting to users. Therefore, in a wafer inspection process,numerous repeating defects may be found, some of which may be “nuisancedefects,” and users will have to analyze these repeater defects indefect classification and review. In this manner, applying designerintent data to reticle inspection without also adapting wafer inspectionprocesses to use designer intent principles will pose real problems forwafer inspection, defect classification and review. As a result, thewafer inspection results may be skewed by permissible wafer defectsresulting from permissible reticle defects. In addition, the accuracyand throughput of defect classification and review may be significantlyreduced. The method described herein, however, advantageously provides amethod for determining which defects are “critical defects” and whichdefects are merely nuisance defects. In this manner, the methoddescribed herein prevents wafer inspection systems or processors frombeing flooded with numerous false defects caused by permissible reticledefects. Therefore, the method described herein provides waferinspection results that may be more clearly analyzed and utilized.

As used herein, the term “nuisance defects” generally refers to defectson a wafer that do not alter a pattern formed on the wafer such thatelectrical elements formed from the pattern will have one or morecharacteristics within a predetermined range for the characteristics. Incontrast, as used herein, the term “critical defects” generally refersto defects on a wafer that alter a pattern formed on the wafer such thatelectrical elements formed from the pattern will have one or morecharacteristics outside of a predetermined range for thecharacteristics. In some embodiments, critical defects may bedistinguished from nuisance defects or other “non-critical defects” bycomparing the defects or features on the patterned wafer that areaffected by the defects to design limits for the patterned wafer.Critical defects may be classified as those defects that alter thepatterned wafer such that it has one or more characteristics outside ofthe design limits.

The method may also include patterning a wafer using the reticle, asshown in step 26. Patterning a wafer generally includes forming a layerof a resist on the wafer. The wafer and the layer of resist formedthereon may be placed in an exposure tool. The exposure tool generallyexposes the layer of resist by directing light through the reticle andonto the resist. The exposure tool may be a scanning projection systemor a step-and-repeat system, also called a “stepper.” The exposure toolmay include any exposure tool known in the art such as toolscommercially available from Nikon, ASM Lithography, Canon, or IntegratedSolutions, Inc. After the resist has been exposed, the wafer may bedeveloped such that a portion of the resist is removed. The remainingportions of the resist form a pattern on the wafer.

The method further includes inspecting the wafer, as shown in step 28.The wafer may be inspected using any method known in the art. Forexample, the wafer may be inspected by illuminating the wafer at anoblique angle of incidence and detecting light scattered from the wafer.Alternatively, or in addition, the wafer may be inspected by detectinglight specularly reflected from the wafer. In addition, the wafer may beinspected using optical techniques or non-optical techniques such as ane-beam inspection technique. The wafer may also be inspected using anyinspection system known in the art. Examples of suitable inspectionsystems include the 2351 system, the AIT XP system, the AIT TFH system,the eS25 system, the Surfscan SP1^(DLS) system, the Viper 2401 system,and the Viper 2430 system, which are all available from KLA-Tencor. Insome embodiments, the method may not include inspecting the wafer. Insuch embodiments, the method may include obtaining wafer inspection datafrom a wafer inspection system or a fab database. The wafer inspectiondata may be obtained from a wafer inspection system or a fab database asdescribed and shown in FIG. 2.

In addition, the method includes identifying nuisance defects on thewafer, as shown in step 30. The nuisance defects may be identified basedon inspection data produced by inspection of a reticle that was used toform a pattern on the wafer prior to inspection of the wafer. Forexample, nuisance defects may be formed on the wafer as a result ofdefects on the reticle that were determined to be permissible reticledefects. In this manner, the method may include identifying reticledefects that were determined to be permissible and locatingcorresponding wafer defects that result from these permissible reticledefects. Since it is known that these defects are permissible and willnot reduce yield of semiconductor devices, the processor configured toperform the method may be provided with data relating to permissiblereticle defects such as defect location and other defect characteristics(i.e., size, aspect ratio, etc.), which may be generated during thereticle inspection process. For example, a processor configured toperform the method may receive reticle inspection data for the reticlethat was used to pattern the wafer as described above. The processor mayidentify wafer defects corresponding to the permissible reticle defectsand may not flag these defects as “actual defects.” The term “actualdefects” is used herein to refer to defects on a wafer that are not aresult of permissible reticle defects.

In addition, as shown in FIG. 1, the method may include translatingcoordinates of a location of a defect on a reticle to coordinates of oneor more locations on a wafer, as shown in step 24. In some embodiments,the coordinates of a location of a permissible reticle defect may betranslated to coordinates of one or more locations on a wafer. In thismanner, if a defect is detected at these one or more locations on thewafer, the defect may be identified as a permissible wafer defect, or a“nuisance defect.” In other embodiments, if the effect of a reticledefect on a patterned wafer is unknown, the coordinates of the reticledefect may be translated to coordinates of one or more locations on awafer. The wafer may be exposed with the reticle, and the one or morelocations on the wafer may be inspected or otherwise analyzed todetermine the printability of the reticle defect or the effect that thereticle defect has on the printed pattern.

In other embodiments, the method may include identifying locations on awafer in which nuisance defects will be formed based on inspection dataproduced by inspection of a reticle. Such a method may also includeselecting one or more parameters for wafer inspection such that thelocations in which the nuisance defects will be formed are notinspected. In a similar manner, the method may include selecting one ormore parameters for wafer defect review such that the nuisance defectsare not reviewed. In yet another embodiment, the method may includeselecting one or more parameters for wafer defect analysis such that thenuisance defects are not analyzed.

In one embodiment, defect coordinates between a point on a reticle and acorresponding point on a wafer may be translated automatically. Incontrast, currently, translation of coordinates between a reticle and acorresponding wafer is usually performed in a non-automatic manner. Forexample, non-automatic translation of coordinates may be performedmanually using a spreadsheet. Automatic translation of coordinates,however, may be particularly advantageous in connection with analysis ofdefects based on design information. One embodiment of coordinatetranslation may be implemented using X-LINK, which is commerciallyavailable from KLA-Tencor, and automating the X-LINK capability forcreating translated coordinates from reticle coordinates and wafercoordinates. In such an embodiment, reticle defect images may also besent to a processor configured to analyze the defects based on thedesign information. In some embodiments, translating the coordinatesfrom a reticle to a wafer may also include automatically verifying theaccuracy of the translation.

In some embodiments, reticle defects may be determined to be permissiblereticle defects based on designer intent data as described above. Inanother embodiment, the method may include using the designer intentdata in combination with the data generated by inspection of the waferto identify nuisance defects on the wafer. For example, the designerintent data may be used to indicate different types of regions,features, or portions of features on the reticle. Therefore, thedesigner intent data may be similarly applied to corresponding regions,features, or portions of features on a wafer printed with the reticle.In this manner, the defects may be identified as nuisance defects orcritical defects based on the types of regions, features, or portions offeatures on the wafer in which the defects are located. As such, thedesigner intent data may be used to identify nuisance defects on thewafer which may or may not be formed on the wafer as a result ofpermissible reticle defects. For example, the designer intent data maybe used to identify nuisance defects on the wafer that are a result of adefective resist layer.

In one such example, the method may include using designer intent datacorresponding to “dummy structures” such as chemical-mechanicalpolishing (CMP) dummy pads to identify areas on a wafer that a user doesnot care about the defectivity of (i.e., “don't care areas” or DCA). Asused herein, the term “dummy structures” is used to refer to patternedfeatures that do not form an electrical element of a semiconductordevice. As described above, wafer inspection faces two main challenges:detecting the defects of interest and filtering out the nuisancedefects. When CMP dummy pads are added to the layout of a design, thesecond challenge increases in significance since the time spent onfiltering nuisance defects detected on dummy pads may increasesignificantly. In addition, as the number of dummy pads increases, thenumber of nuisance defects that may be detected on the dummy pads willincrease. Furthermore, as the number of copper-based interconnectsincluded in an IC increases, the number of layers of the IC that includeCMP dummy pads increases significantly.

Manually identifying DCA around regions of CMP dummy pads may beextremely time consuming. The method described herein, however, reducesthe time required for filtering nuisance defects or manually generatingDCA by using layout tools or a processor to generate the DCA around thedummy pads for inspection purposes. Additionally, the dummy pad areasmay be filtered out for inspection purposes while maintaining thesensitivity of defect inspection on circuit areas of the overallpattern.

FIGS. 3 a-3 d illustrate one example of how individual layer data for anIC can be manipulated to identify DCA on a wafer. The individual layerdata manipulated in this example is layer data for the first metal (M1)layer of the IC. However, it is to be understood that similarmanipulation of individual layer data may be performed for any layer ofan IC. Initially, the individual layer data may be selected from a GDSIIfile. By performing an AND operation between the individual layer dataand the reference frame, the original mask data may be generated for theM1 layer, as shown in FIG. 3 a. The dummy pads may then be generated inregions of the M1 layer where there is not a pattern by performing a NOToperation between the frame and the layer data, as shown in FIG. 3 b.Therefore, a simple sequence of Boolean operations allows easygeneration of dummy pads for the M1 layer.

As shown in FIG. 3 c, by performing an AND operation between the dummydata and the reference frame a first DCA (DCA1) may be identified.However, it may be advantageous to inspect some portions of DCA1 tocheck for defects that may adversely affect a layer above or below thislayer. For example, most times a defect on a dummy pad by itself isinsignificant from a circuit performance perspective. However, some ofthese defects may contribute to defects at another or the next layer,where they may cause disruption of a real circuit pattern. Manualgeneration of the DCA, however, is performed without any knowledge ofthe layers to be formed on top or below the layer for which the DCA isbeing determined. In contrast, by performing a NOT operation between theDCA1 data and data for a layer above or below this layer (i.e., in thecase of the M1 layer, data for the M2, M3, and even M4 layers), thedummy area may be further filtered to determine the actual DCA data(i.e., DCA2). For example, as shown in FIG. 3 d, the dummy areas thatoverlap with layer data of the M2 layer may be removed from DCA1 sincedefects on these overlapping dummy pads may adversely affect one or morecharacteristics of features on the M2 layer.

The method may also include altering the size of the DCA. For example,some of the DCA generated by the Boolean operations may have dimensionsthat are too small or too large to be effectively managed by aninspection system stage assembly and/or image computer. After generationof the DCA, the DCA may be sized down or up through the minimumdimension (i.e., x μm) that the inspection tool can handle (i.e.,DCA3=DCA2−x or DCA3=DCA2+x). In addition, DCA that are relatively smallmay be eliminated from the DCA data for an entire layer. In this manner,certain DCA may be sized or eliminated from the DCA data for a layerwhile allowing identification of defects in the DCA that may causedefects on another layer of the IC.

The DCA data may be provided to a reticle inspection system, a waferinspection system, a defect review system, and/or an analysis system. Inanother embodiment, designer intent data or information about thecriticality associated with different areas of the wafer may be sent toa reticle inspection system, a wafer inspection system, a wafer defectreview tool, and/or a wafer defect analysis tool. The reticle inspectionsystem or the wafer inspection system may use the DCA data and/or thedesigner intent data to detect actual defects on a reticle or a wafer byfiltering out nuisance defects detected in the DCA or by not performinginspection in the DCA at all. In this manner, the wafer inspector and/orreticle inspector may be configured to inspect only the areas of thewafer that matter or that matter the most.

In a similar manner, the defect review system may use the DCA dataand/or the designer intent data to review only the areas of the waferthat matter (i.e., non-DCA areas) or that matter the most. In otherwords, one or more parameters for wafer defect review may be determinedbased on the criticality associated with different areas of the wafer.In one embodiment, the one or more parameters may be selected such thatonly defects located in critical portions of the wafer are reviewed. Theparameters may also be different for different critical portions of thewafer. In addition, the defect review system may use the DCA data ordesigner intent data to distinguish between actual defects and nuisancedefects. In another example, the defect analysis system may use the DCAdata and/or the designer intent data to analyze only areas of the waferthat matter (i.e., non-DCA areas) or that matter the most. For example,one or more parameters for wafer defect analysis may be determined basedon the criticality associated with different areas of the wafer. The oneor more parameters may be selected such that only defects located incritical portions of the wafer are analyzed. The parameters may also bedifferent for different critical portions of the wafer. Furthermore, theanalysis station may use the DCA data or the designer intent data todistinguish between actual defects and nuisance defects.

In a different embodiment, data generated by a reticle or waferinspection system may be transmitted to a processor configured togenerate the DCA. The processor may use data generated by inspection incombination with the DCA data to identify actual defects on a reticle orwafer by filtering out defects detected in the DCA or by not performingdefect detection on inspection data corresponding to the DCA.

The method may also include separating nuisance defects on the waferfrom actual defects on the wafer, as shown in step 32. In oneembodiment, the nuisance defects may be separated from the actualdefects simply by not flagging or identifying the nuisance defects asdefects at all. In this manner, data generated during wafer inspectionwill not include data representative of the nuisance defects. In otherembodiments, nuisance and actual defects may be assigned differentdesignations such that both types of defects are recorded and can beseparated based on the different designations. In another embodiment, anuisance defect file or list may be generated separately from an actualdefect file or list. The nuisance defect file or list may or may not beaccessible to the user. For example, in some instances, the user may beinterested in only the actual defects and, therefore, will have no needfor the nuisance defect file or list. In other instances, the user mayaccess the list for further processing or analysis of the nuisancedefects such as verification of the permissibility of the nuisancedefects, determination of the effects of the nuisance defects onsemiconductor device yield, or for display of the nuisance defectsoverlaid with other data. In other embodiments, the nuisance defect datamay be used for tool-to-tool comparisons or calibrations. For example,the nuisance defect data may be used to calibrate or compare inspectionsystems of different make and model or inspection systems of the samemake and model. If different makes and/or models of inspection systemsare to be compared, the nuisance defects may be stored as files having acommon data structure such as KLARFF.

As shown in step 34, the method may also include processing datarepresentative of the actual defects, but not data representative of thenuisance defects. For example, the data representative of the nuisancedefects may not be further processed, classified, reviewed, or analyzedsince the defects were previously determined to be permissible. Byeliminating processing of the nuisance defect data, processing theactual defect data will be simpler, possibly more accurate, and quickerProcessing data representative of the actual defects may include, but isnot limited to, determining a lateral dimension of the actual defects,determining a material of the actual defects, classifying the actualdefects, reviewing the actual defects, and analyzing a root cause of theactual defects.

In some embodiments, the method may include generating a two-dimensionalmap of the wafer, as shown in step 36. In one embodiment, the nuisancedefects may be shown in the map along with other defects detected on thewafer. In such an embodiment, the nuisance defects may be distinguishedfrom other defects in the map by one or more different designations. Inother embodiments, the nuisance defects may not be shown in the map. Themap may, therefore, illustrate only actual defects detected on thewafer. In this manner, the map may be more quickly analyzed by a user orby a processor since the nuisance defects have been eliminated. Thetwo-dimensional map may illustrate the entire wafer (i.e., a wafer map)or only a portion of the wafer (i.e., one or more die maps). In oneembodiment, the method may include generating more than onetwo-dimensional maps illustrating various portions of the wafer. Inaddition, the method may include generating one or more two-dimensionalmaps illustrating the critical portions of the wafer. The types of thevarious portions of the wafer may be illustrated in the maps usingdifferent colors, flags, or other indicia. In some embodiments, thetwo-dimensional map may be overlaid with other data such as PROLITHdata, defects, and inspection areas.

In additional embodiments, the method may include determining if thenuisance defects affect the yield of semiconductor devices that areultimately fabricated on the wafer, as shown in step 38. For example,the actual impact of the permissible reticle defects on yield may beanalyzed from time to time. In one embodiment, the actual impact of thepermissible reticle defects may be analyzed by electrical testing thatis performed on electrical elements formed on the patterned wafer. Theelectrical testing may be performed before or after completesemiconductor devices are formed from the electrical elements. In otherembodiments, the actual impact of the permissible reticle defects may beanalyzed by simulation of the electrical characteristics of electricalelements that will be formed from the patterned wafer. The simulationprogram may be provided with specific information about the waferdefects that resulted from the permissible reticle defects. The specificinformation may include results of metrology, inspection, or otheranalytical testing.

In other embodiments, the method may include analyzing the nuisancedefects to determine if the permissible reticle defects were correctlyclassified, as shown in step 40. For example, the effect that thenuisance defects have on yield of semiconductor devices fabricated onthe wafer, which may be determined in step 38, may be used to determineif the reticle defects are actually permissible. In some embodiments,analyzing the nuisance defects to determine the permissibility of thereticle defects may include further metrology or experimental techniquessuch as high-resolution imaging. In other embodiments, analyzing thenuisance defects to determine the permissibility of the reticle defectsmay include analyzing or processing data representative of the nuisancedefects. For example, modeling may be used to determine the effect thata nuisance defect will have on electrical characteristics of a deviceformed on the wafer.

If the permissible reticle defects were not correctly classified, themethod may include determining if the reticle should be analyzed,reworked, or disposed, as shown in step 42. For example, the reticle maybe analyzed to generate information about the incorrectly classifieddefects such as size, material, phase and transmission characteristics,and proximity to other features on the reticle. In addition, reworkingthe reticle may include repairing the incorrectly classified defects orremoving the incorrectly classified defects from the reticle. The repairprocess may include chemically assisted laser removal, laser inducedshock wave removal, or particle beam assisted repair. An example of achemically assisted laser removal tool is illustrated in “ChemicallyAssisted Laser Removal of Photoresist and Particles from SemiconductorWafers,” by Genut et al. of Oramir Semiconductor Equipment Ltd., Israel,presented at the 28^(th) Annual Meeting of the Fine Particle Society,Apr. 1-3, 1998, which is incorporated by reference as if fully set forthherein. An example of a laser induced shock wave removal tool isillustrated in U.S. Pat. No. 5,023,424 to Vaught, which is incorporatedby reference as if fully set forth herein. A particle beam assistedrepair tool may be configured to perform a focused ion beam (“FIB”)technique, which is known in the art. Such a particle beam assistedrepair tool is commercially available from, for example, MicronCorporation, Peabody, Mass. Alternatively, reworking the reticle mayinclude cleaning the reticle using a wet or dry cleaning process such asetch or stripping processes. If the incorrectly classified defects arenot repairable, the reticle may be disposed. In addition, the reticlemay be disposed of if the number of incorrectly classified defectssubstantially increases the cost of repair. The method shown in FIG. 1may include any other steps of any other methods described herein.

FIG. 4 is a flow chart illustrating a computer-implemented method thatincludes detecting defects on a wafer by analyzing data generated byinspection of the wafer in combination with data representative of areticle. The method includes obtaining data representative of thereticle, as shown in step 44. The data representative of the reticle mayinclude macro level information (like the SRAM). The macro levelinformation may include repeating small figures (like cells) amassedinto intermediate level figures (like memory pages), which can bebrought up together to the macro level. The data representative of thereticle may also be discrete micro features in the logic. Such data maybe described in MEBES files, GDSII files or other standard filedescriptions of the reticle. The files may include designer intent dataas described above such as designations that distinguish betweendifferent yes of portions of the reticle, features, or portions offeatures on the reticle.

The method may also include determining parameters of wafer inspection,as shown in step 46. For example, determining parameters of waferinspection may include identifying different types of portions of thewafer, features, or portions of features on the wafer that correspond tothe different types of portions of the reticle, features on the reticle,or portions of features on the reticle based on the data representativeof the reticle. In one embodiment, the method may also includedistinguishing between different portions of the wafer, as shown in step52. The different portions of the wafer may be determined based on thedata representative of the reticle. In particular, the differentportions of the wafer may be determined based on the designations thatidentify different types of portions of the reticle, which can becorrelated to the different portions of the wafer as described herein.For example, the different portions of the reticle may be correlatedwith areas on the wafer in which these different portions of the reticleare printed. In this manner, different portions of the wafer may beidentified as critical or non-critical.

Alternatively, the critical portions of a wafer may be identified basedon the criticality associated with different areas of the wafer. Thecriticality of the different areas of the wafer may be reflected in thedesigner intent data, which is described further above. In this manner,different portions of the wafer, features, or portions of features onthe wafer may be identified as critical or non-critical.

Different parameters of inspection may be associated with the differentportions of the wafer, features, or portions of the features on thewafer. For example, the parameters may be selected such that criticalportions having different criticalities are inspected with differentparameters. The parameters that may be varied may include, but are notlimited to, sensitivity and throughput. In one example, if a portion ofthe wafer is identified as non-critical, this portion of the wafer maybe inspected with less sensitivity and higher throughput than a criticalportion of the wafer. In another example, if a feature of the wafer isidentified as critical, this feature of the wafer may be inspected withhigher sensitivity and lower throughput than a non-critical feature ofthe wafer. In this manner, the parameters of wafer inspection may bevaried across the wafer to balance the trade-off between sensitivity andthroughput without reducing the accuracy of detection in the criticalportions of the wafer. Furthermore, the parameters for inspection of thewafer may be selected such that only the critical portions of the waferor the portions of the wafer that matter are inspected. In this manner,adequate sensitivity of inspection in the critical portions or theportions that matter may be maintained while the overall throughput ofwafer inspection may be increased.

Other parameters of inspection may be varied in a similar manner.Additional parameters that may be varied include the cell size used inbright field array inspection and the point spread function that is usedfor an array detector such as that included in the AIT systems availablefrom KLA-Tencor. In addition, the parameters of inspection may be variedfrom wafer to wafer. The method may also include setting the parametersfor wafer inspection. Setting the parameters for wafer inspection mayinclude setting up the hardware and/or the software of a waferinspection system.

As shown in step 48, the wafer may be inspected using the parametersdetermined in step 46. The wafer may be inspected as described above. Inaddition, the wafer may be inspected using any of the wafer inspectionsystems described above. In some embodiments, the wafer inspection maybe performed as a process monitor inspection. Such an inspection may beperformed during a process or after a process has been performed on awafer. In addition, such wafer inspection may be carried outautomatically by an inspection system that is suitably configured toautomatically inspect a wafer during or after a process. The results ofthe process monitor inspection may be used to analyze the process andmay also be used to alter one or more parameters of the process asdescribed herein. Inspection of the wafer produces data generated byinspection of the wafer, as shown in step 50.

In addition, the method may include determining parameters for detectionof defects on the wafer, as shown in step 54. Determining parameters fordefect detection may be based on the types of the portions of the wafer.The parameters that may be varied may include, for example, a thresholdvalue, a type of algorithm, and/or an inspection method (i.e., array orrandom). In some embodiments, predetermined thresholds may be associatedwith different types of portions of the wafer. In this manner, apredetermined threshold may be selected for defect detection in aportion of the wafer based on the type of the portion of the wafer. Inone example, if a portion of the wafer is determined to be a criticalportion of the wafer based on the reticle information or designer intentdata, a lower threshold may be used for this portion of the wafer thanthe threshold that is used for a non-critical portion of the wafer. Inthis manner, the sensitivity or method of defect detection may bedifferent in critical and noncritical portions of the wafer. Inaddition, parameters of detection may be selected such that particulardefects may be disregarded even though they are detected. For example,the parameters of detection may be set such that nuisance defects aredisregarded even if they are detected. In this manner, the method mayinclude setting parameters for detection in the processor or an imagecomputer for a “difference threshold” to detect defects in differentregions (i.e., region based multi-thresholding). As such, nuisancedefects on the wafer may not be classified or detected as actual defectson the wafer.

According to another embodiment, information about a reticle or designerintent data and the fault-tolerance of the design may be used todetermine which defects may be discarded or classified as nuisancedefects. For example, detecting defects may include discarding defectsor events in one portion of the wafer that have a lateral dimensionsmaller than the predetermined threshold associated with this portion ofthe wafer if other features in this portion of the wafer have a lateraldimension greater than the predetermined threshold. Such defects may bediscarded since such defects may not be “killer defects.” In a differentexample, defects in one portion of the wafer may be discarded if anelement of a circuit in this portion of the wafer or in a section of thedesign has a predetermined amount of redundancy and if the defects inthis portion of the wafer do not exceed a predetermined densitythreshold. In one such embodiment, the circuit may be tested uponcompletion to identify defective redundant elements. In addition, thecircuit may be reconfigured to retain only the non-defective redundantelements.

In another example, different algorithms may be used for critical andnon-critical portions of the wafer. As such, the parameters of defectdetection may be varied across the wafer. In addition, the parameters ofdefect detection may be varied from wafer to wafer. Other parameters ofdetection may be varied in a similar manner. For example, the parametersof detection may be selected such that detected defects may beautomatically tagged with designations that indicate the portion of thewafer or the type of the portion of the wafer in which the defects arelocated. Such designations may be used to determine appropriate analysisof the defects such as critical dimension (CD) measurement, scanningelectron microscopy analysis, profile analysis, or material analysis. Ina similar manner, defects may be automatically assigned designationsthat directly indicate the type of analysis to be carried out onindividual defects.

In one embodiment, correlating different portions of the reticle withdifferent portions of the wafer may include translating coordinates ofthe reticle to coordinates of the wafer, as shown in step 56. Inaddition, the method may include translating coordinates of a locationof a defect detected on a reticle to coordinates of locations of one ormore defects on the wafer. Translating coordinates of the reticle tocoordinates of the wafer may be performed as described above.

The method also includes detecting defects on the wafer, as shown instep 58. Detecting the defects on the wafer may be performed using thedata generated by inspection of the wafer in combination with the datarepresentative of the reticle. For example, defect detection may beperformed using the data generated by inspection of the wafer incombination with the parameters for detection that were determined basedon the data representative of the reticle.

The method may also include obtaining data representative of a layer onthe wafer, as shown in step 60. The layer may be above or below thelevel of the wafer, which is being inspected. In one embodiment, defectdetection may be performed by analyzing the data generated by inspectionof the wafer in combination with the data representative of the reticleand data representative of at least one layer of the wafer above orbelow the one level of the wafer. This combination of data may also beused to distinguish between critical defects and non-critical defectssince features of a device that are above or below a defect may, in someinstances, alter the criticality of a defect. For example, a defect thatis not critical with respect to the level on which the defect is locatedmay be critical with respect to features that are located above or belowthe defect in another layer of the wafer.

In one example, if the layer being inspected is used to form the M3layer of an IC, information about the M2 layer and/or the M4 layer ofthe IC may be obtained and used for defect detection. In this manner,the method may include utilizing design information for multiple layersof an IC design, including one or more layers above and/or below thelayer being currently processed or inspected, to identify criticaldefects and filter out non-critical defects. For example, the “don'tcare areas” of a layer of an IC may be determined based on data ofanother layer of the IC, as described above with respect to FIGS. 3 a-3d. In addition, defects detected in the “don't care areas” may bediscarded. Therefore, the criticality of a defect on the wafer may beidentified based on the criticality of the portion in which the defectis located and data representative of at least one layer of the waferabove or below the level of the wafer on which the defect is located. Inaddition, inspection data generated in the “don't care areas” may not beanalyzed during defect detection. Alternatively, the “don't care areas”may not be inspected at all.

In some embodiments, the method may also include generating athree-dimensional representation of the defects detected on one level ofthe wafer. In one such embodiment, the three-dimensional representationmay include a three-dimensional representation of other features on theone level of the wafer and/or at least one layer of the wafer above orbelow this one level. In this manner, the method may include generatingand displaying a three-dimensional composite of design layers next tothe image of the defect under review. In one embodiment, the layer onwhich the defect is located may be highlighted, and any relevant designstructures on this layer may be identified with some sort ofdesignation.

According to one embodiment, reticle design information or designerintent data may be used as a factor to determine subsequent analysis ofa defect. For example, the method may further include determiningprocessing of the defects based on the criticality of the portion inwhich the defects are located, as shown in step 62. The processing mayinclude additional analytical testing of the defects such as criticaldimension (CD) measurements, scanning electron microscopy measurements,or any other metrology, review, or analysis known in the art. In oneembodiment, appropriate processing may be determined based ondesignations assigned to defects during detection as described above.For example, a defect detected using an optical wafer inspection systemmay be located in a critical area of the wafer as indicated by designinformation. In this case, the defect may be reviewed using an e-beamreview tool. Alternatively, if a defect does not appear to fall in acritical area of the wafer as evident from design information, nofurther review of the defect may be performed. In this manner, defectsidentified as critical defects may processed separately fromnon-critical defects.

In some embodiments, processing the defects may include repairing thedefects on the wafer. Repairing defects on the wafer may includesimultaneously repairing multiple defects on the wafer using, forexample, a cleaning process, an etching process, or a CMP process.Alternatively, repairing defects on the wafer may include repairing thedefects one at a time using, for example, a FIB technique. Differenttypes of defects may be subjected to different repair processes. Forexample, critical defects may be subjected to a more accurate repairprocess than non-critical defects. In this manner, critical defects andnon-critical defects may be separately repaired. In addition, only aportion of all of the defects detected on a wafer may be repaired. Forexample, critical defects may be repaired while non-critical defects maynot be repaired.

In some embodiments, the method may include analyzing the printabilityof defects detected on the reticle, as shown in step 64. For example,defects on the reticle may be correlated to defects or locations on thewafer based on coordinates of the reticle that are translated tocoordinates of the wafer. In addition, the defects or locations on thewafer that correlate to reticle defects may be identified and analyzedto determine how the reticle defects affect the patterned wafer. Theprintability of permissible reticle defects may be determined to confirmor contradict the permissibility of these defects. In addition, theprintability of reticle defects that have not been identified aspermissible may also be analyzed in this manner.

The method may also include classifying the defects detected on thewafer as critical defects or non-critical defects, as shown in step 66.In one embodiment, the defects may be classified as critical ornon-critical defects based on the portion of the wafer in which thedefects are located. In a different embodiment, the defects may beclassified as critical or non-critical defects based on the proximity ofthe defects to a critical or non-critical feature or portion of afeature on the wafer. For example, defects that are located within about100 nm of a critical feature may be identified as critical, but defectsthat are located at least about 1000 nm from the critical feature maynot be identified as critical. These distances are merely illustrativeand may vary greatly depending upon, for example, the type of thefeature (i.e., a gate structure or a contact structure) and the size ofthe defects. In an additional embodiment, defects on the wafer thatcorrelate to permissible defects on the reticle may be identified asnon-critical or nuisance defects. In another embodiment, the defects maybe classified as critical or non-critical defects based oncharacteristics of the defects such as phase, transmission, and lateraldimension. The parameters for classification may also be determinedbased on the portion of the wafer in which the defects are located, orthe criticality of the portion of the wafer in which the defects arelocated. In this manner, the portion of the wafer in which the defect islocated may be a factor in assigning a classification to a defect.Classification of the defects may be performed by an image computer orby post-detection software. Classifying the defects may also includeassigning other “types” to the defects. For example, classifying thedefects may include identifying the defects as scratches, particles, orpits. In some embodiments, classifying the defects may include using adefect source analysis (DSA) algorithm, which is known in the art, orany other algorithm or defect classification method known in the art.

The method may also include assigning designations to the defects, asshown in step 68, if the designations are not already assigned duringdetection as described above. The designations may be associated withthe different portions of the wafer in which the defects are located. Inaddition, the designations assigned to the defects may be based on thecriticality of the portion of the wafer in which the defects arelocated. The designations may include flags, alphanumeric characters, orany other indicia that can be used to distinguish between differenttypes of defects. Data representative of the defects and thedesignations assigned to the defects may be stored in a single file.Alternatively, data representative of the defects may be stored in onefile, and the designations assigned to the defects may be stored in adifferent file.

As shown in step 70, the method may include separating the criticaldefects from the non-critical defects. Separating the critical defectsfrom the non-critical defects may be performed as described above. Insome embodiments, the method may include removing data generated byinspection of the wafer at coordinates on the wafer that correspond to alocation of a permissible reticle defect from the data generated by thewafer inspection. In addition, the method may include processing thedata representative of the critical defects and the non-critical defectsseparately, as shown in step 72. Processing the data representative ofthe critical and non-critical defects separately may be performed asdescribed above.

As shown in step 74, the method may further include analyzing a processperformed on the wafer based on information about the critical defectsand the non-critical defects. Use of designer intent data allowsidentification of critical defects and filtering out of non-criticaldefects for the purposes of inspection and review as described above. Inone embodiment, however, analyzing and resolving problems withmanufacturing processes utilizes both critical and non-critical defectinformation. In a different embodiment, non-critical defect data may beselectively used for process analysis and troubleshooting. For example,the method may include analyzing the lithography process used to patternthe wafer with the reticle. In addition, the information about thecritical defects and the non-critical defects may be used to alter oneor more parameters of the lithography process. For example, the methodmay include altering one or more parameters of the lithography processusing a feedback control technique. The one or more parameters of thelithography process may be altered to reduce the number of criticaldefects that are produced on additional wafers processed using thereticle. The method shown in FIG. 4 may include any other steps of anyother methods described herein.

FIG. 5 is a flow chart illustrating one embodiment of acomputer-implemented method for selectively using defect information toanalyze manufacturing processes. In current practice, foundries, or ICmanufacturing facilities, inspect and review defects occurring on wafersthroughout the various IC manufacturing stages to obtain acharacteristic defect distribution. This defect distribution may then beused for various purposes including predicting yield and identifying andaddressing process limitations. A limitation of this approach is thatthe defect distribution fails to ignore defects that do not have adverseeffects upon the operation of the respective completed IC devices. Thecomputer-implemented method described herein addresses this limitationby refining the defect distribution to provide a more accurateprioritization of defects relevant to the analysis of the manufacturingprocesses.

According to one embodiment, a computer-implemented method fordetermining a property of a manufacturing process may include obtainingdefect information generated by wafer inspections performed at differenttimes during the manufacturing process. The defect information generatedby each inspection may be stored. For example, the defect informationmay be stored in a memory medium, a database, or a fab database. Asshown in FIG. 5, the method also includes identifying bad die on a waferprocessed using the manufacturing process, as shown in step 76.Identifying bad die on the wafer may include performing functionaltesting on the die at the end of the manufacturing process.Alternatively, identifying bad die on the wafer may include performingelectrical testing on the die at some point during the manufacturingprocess. The bad die may contain one or more electrical elements thathave functionality outside of a predetermined range.

In addition, the method includes identifying different portions ofdefects on the wafer, as shown in step 78. In one embodiment, differentportions of defects on a wafer may be identified based on data generatedby inspection of the wafer in combination with informationrepresentative of a design of one or more electrical elements in the haddie. The inspection data may include data generated by multipleinspections of the wafer (i.e., inspection performed at different timesduring the manufacturing process). One portion of the defects may altera characteristic of a device formed by the one or more electricalelements such that the characteristic is outside of predeterminedlimits. For example, design information may be used to efficiently andaccurately analyze the defect information for the bad die to identifycritical defects while selectively ignoring non-critical defects. Thecritical defects may be distinguished from the non-critical defects asdescribed herein. In another example, design information may be used tofilter out defects identified during wafer inspection or review thathave an impact upon the final IC device that is absent or below acertain threshold. The resulting defect distribution provides a moreaccurate measure of the number and types of defects that are relevant tothe manufacturing process.

The method further includes determining a property of the manufacturingprocess based on one portion of the defects, as shown in step 80. Forexample, the property of the manufacturing process may be determinedbased on the critical defects, but not the non-critical defects. In oneembodiment, the property of the manufacturing process is a kill ratio ofthe portion of defects. In another embodiment, the property of themanufacturing process is a yield of the manufacturing process. Byremoving certain non-critical defects from consideration, one embodimentof the computer-implemented method facilitates a more accuratedetermination of the “kill ratio” characteristic of the manufacturingprocess, which in turn enables a more precise estimation of thecharacteristic yield.

The method may also include altering one or more parameters of themanufacturing process based on the property of the manufacturingprocess, as shown in step 82. One or more parameters of themanufacturing process may be altered using a feedback control technique.Since the parameters may be determined based on a more accuratedetermination of the kill ratio or yield of the manufacturing process,the performance of the manufacturing process using the alteredparameters may be significantly improved. The manufacturing process maybe analyzed and altered in such a manner a number of times to reduce thekill ratio and to increase the yield of the manufacturing process evenfurther. The method shown in FIG. 5 may include any other steps of anyother methods described herein.

FIG. 6 is a flow chart illustrating a computer-implemented method thatincludes altering a design of an IC based on data generated byinspection of a wafer performed during a manufacturing process.According to one embodiment, the method may be used for enhancing thedesign process of an IC device based on defect information obtainedduring the manufacturing process for the IC device. The defectinformation may be analyzed in terms of the design information. Themethod provides a feedback method in which the design and manufacturingphases of an IC device are progressively optimized based on designinformation.

Currently, defect inspection and review during the manufacturing phaseof an IC device produces large amounts of defect-related data for eachmanufacturing process. Foundries generally limit use of this defect datato immediate troubleshooting of process issues with the goal ofeliminating the defects in subsequent batches of IC devices. Dependingon various constraining limitations imposed by the characteristics ofthe IC devices being manufactured and by the processes employed duringthe manufacturing phase, however, further improvement of the processesmay become difficult and expensive at some point, with a reduced impacton defect reduction. For example, one or more processes performed duringthe manufacturing phase of a microprocessor may be unable to reliablymeet critical dimension requirements.

The computer-implemented method includes designing an IC, as shown instep 84. The IC may be designed using any method known in the art. Themethod also includes processing a wafer using a manufacturing process,as shown in step 86. The manufacturing process may include a number ofindividual processes such as deposition, lithography, etch,chemical-mechanical planarization, plating, ion implantation, cleaning,and epitaxy. In addition, the manufacturing process may includeperforming some of the individual processes more than once. As shown instep 88, the method includes inspecting the wafer during themanufacturing process. The wafer may be inspected multiple times duringthe manufacturing process. For example, the wafer may be inspected aftera lithography process, after an etch process, after achemical-mechanical planarization process, and/or after a cleaningprocess. In some cases, the wafer may be inspected during one or more ofthe individual processes.

Critical and non-critical defects may be detected on a wafer during theinspection of the wafer. As shown in step 90, the method may includedistinguishing between critical and non-critical defects on the waferbased on the IC design. For example, the IC design may includedesignations that may indicate different portions of the design. Thedesignations may be further configured as described above. In oneembodiment, the criticality of the defects may be determined based onthe portion of the design in which the defect is located. In anotherembodiment, the critical defects may include defects that may alter oneor more characteristics of the IC. In contrast, the non-critical defectsmay include defects that will not substantially alter one or morecharacteristics of the IC.

In some embodiments, the method may include separating critical defectsfrom non-critical defects, as shown in step 92. In this manner, thecritical defects may be easily processed separately from thenon-critical defects. The critical and non-critical defects may beseparated as described above. In addition, the method includes alteringthe design of the IC based on the defects detected on the wafer, asubstantial portion of which include critical defects, as shown in step94. In this manner, using the design information, the method selectivelyignores defects that are not critical to the functionality of thecompleted IC device thereby reducing or eliminating the limitations ofthe currently used methods. As shown in FIG. 6, altering the design ofthe IC may be performed using a feedback control technique.

In one embodiment, the design of the IC may be altered to reduce thenumber of critical defects that are formed during the manufacturingprocess. In another embodiment, the method may include determining ayield of the manufacturing process based on the critical defects, asshown in step 96. In such an embodiment, the design of the IC may bealtered to increase the yield of the manufacturing process. In someembodiments, the method may include identifying one or more individualprocesses of the manufacturing process that result in at least some ofthe critical defects being formed on the wafer, as shown in step 98.Therefore, using the design information, the method permits a moreaccurate identification of the truly-limiting processes during themanufacturing phase.

According to one embodiment, once these limiting processes areidentified with an improved degree of confidence, information aboutparticular characteristics of the design that tend to induce failure ofthe limiting processes is used to refine the design of the IC device. Inthis manner, the design of the IC may be altered in response to theindividual processes that produce critical defects on the wafer. In onesuch embodiment, the method may also include determining if the designof the IC contributes to the formation of the critical defects, as shownin step 100. In addition, the design of the IC may be altered to reducea number of the critical defects that are formed during the individualprocesses.

An enhanced design that reduces critical defects during themanufacturing phase could provide enhanced sensitivity and throughputduring subsequent inspection and review. This feedback method forenhancing the IC design phase may be performed more than one time toprogressively improve the yield of the manufacturing phase. In anadditional embodiment, the manufacturing process may be altered based onthe information about defects that were detected on the wafer. Themethod shown in FIG. 6 may include any other steps of any other methodsdescribed herein.

FIG. 7 is a schematic diagram illustrating storage medium 102. In oneembodiment, the storage medium may be a database. In another embodiment,the storage medium may include any medium suitable for storage of dataknown in the art. Storage medium 102 includes data representative of anIC design 104. Storage medium 102 also includes data representative ofan IC manufacturing process 106. In addition, storage medium 102includes defect data 108 representative of defects detected on a waferduring the IC manufacturing process. The defect data may be filteredsuch that a substantial portion of the defects includes critical defectsthat can alter one or more characteristics of the IC. In particular, thedefect information may be filtered using design information to excludenon-critical defects that have no impact or only a limited impact on thefunctionality of the completed IC device.

In some embodiments, the storage medium may also include datarepresentative of relationships between the critical defects and the ICdesign 110. In particular, the relationships may be relationshipsbetween IC design characteristics and defects that may occur during themanufacturing phase in connection with various manufacturing processes.In one embodiment, the storage medium can be used to alter the IC designbased on the data representative of the IC design 104, the datarepresentative of the IC manufacturing process 106, and defect data 108.In some embodiments, the storage medium may be used to alter the ICdesign using a relationship between the IC design characteristics andthe defects. Therefore, the storage medium may be used during the designphase to enhance the fitness of the design for manufacturability. Inaddition, the storage medium illustrated in FIG. 7 may be used to carryout the method illustrated in FIG. 6.

FIG. 8 is a flow chart illustrating an embodiment of acomputer-implemented method that includes simulating one or morecharacteristics of an IC based on defect data generated by inspection ofa wafer during a manufacturing process. A substantial portion of thedefects includes critical defects that can alter one or morecharacteristics of the IC. In some embodiments, the method may be usedto simulate the impact of the defects on the functionality of a completeIC device. In contrast, currently, IC design tools simulate theperformance of an IC design without using manufacturing processinformation. Instead, such simulations generally focus onnon-process-related relationships such as the relationship betweendesign rules and timing. In addition, tools for simulation of the impactof defects on fully-manufactured IC devices currently only take intoaccount limited information regarding the defects. Consequently, theability to predict the impact of the defects on an IC design isrelatively inaccurate and unreliable. In contrast, the method describedherein provides an enhanced method for simulation of the performance ofan IC design by taking into account manufacturing process information.In addition, the method described herein addresses the limitations ofother simulation methods by utilizing comprehensive defect informationwhile simulating the impact of defects on the functionality of a final,completed IC device. The manufacturing process information and thecomprehensive defect information may be obtained using IC designinformation.

As shown in step 112, the method may include generating data byinspecting a wafer. The wafer may be inspected at any time during amanufacturing process. In alternative embodiments, the method mayinclude obtaining data generated by inspection of a wafer as describedabove. In one embodiment, the data may be generated by inspection andreview performed during various stages of the manufacturing process ofthe IC device. In some embodiments, the information about the defectsmay include coordinates of defect locations on the wafer andthree-dimensional defect profiles. The information about the defects mayinclude, however, any other information about the defects that may begenerated during inspection or review.

The method also includes separating critical defects from non-criticaldefects, as shown in step 114. Critical defects may be separated fromnon-critical defects using designer intent data as described herein. Forexample, the method may include distinguishing between critical defectsand non-critical defects detected during the inspection based on thedesign of the IC. The non-critical defects may be identified as thosedefects that will not substantially alter the one or morecharacteristics of the IC (i.e., defects that are not critical to theperformance of the IC device). In this manner, information about theyield and performance of various processes employed during themanufacturing phase is obtained by selectively ignoring defects that,based on design information, are determined to be not critical to theperformance of the completed IC device.

The method includes simulating one or more characteristics of an ICbased on the defect data, as shown in step 116. In some embodiments, theinformation about the various manufacturing processes obtained above mayalso be used to simulate one or more characteristics of the IC. Theinformation about the various processes obtained above may be used tomore accurately simulate the performance of the design of the IC device.In addition, such preprocessing of the defect information ensures thatthe simulation can be performed more efficiently, faster, and using lesscomputational resources. In a particular implementation, the defect dataused for the simulation includes defect coordinates and athree-dimensional defect profile. The one or more characteristics of theIC may include, but are not limited to, voltage drops, timing slowdowns,partial device failure, and total device failure. The method shown inFIG. 8 may include any other steps of any other methods describedherein.

FIG. 9 is a flow chart illustrating an embodiment of acomputer-implemented method that includes determining placement of apattern on a specimen based on defect data. In one embodiment, themethod includes using design information to selectively match a designpattern to a blank medium exhibiting defects. In an embodiment, thespecimen may be a blank reticle substrate. In an alternative embodiment,the specimen may be a wafer. The wafer may be a blank wafer or a waferprior to having a patterned layer formed thereon. The wafer may,however, have other patterned layers previously formed thereon. Suchpreviously patterned layers may be formed underneath the layer about tobe patterned. However, the computer-implemented method described hereinmay be applied to most cases where a pattern is imprinted or otherwiseimpressed upon a medium or specimen that may exhibit defects, includingany such specimen known in arts other than the semiconductor industry.

As shown in step 118, the method may include generating data byinspecting a specimen, In different embodiments, the method may includeobtaining the data generated by inspection of a specimen as describedabove. The method may also include identifying critical portions of thepattern, as shown in step 120. In some embodiments, identifying criticalportions of the pattern may be based on design information as describedherein. In alternative embodiments, the method may include identifyingcritical portions of the pattern without such design information. Forexample, alignment of the pattern with a blank reticle substrate may beperformed without using the design information.

In addition, the method may include determining placement of the patternon the specimen, as shown in step 122. Determining the placement of thepattern may include laterally translating the pattern, rotating thepattern, scaling the pattern, or any combination thereof. Laterallytranslating the pattern may include laterally translating the pattern inthe x direction and/or the y direction. In one embodiment, determiningthe placement of the pattern may include selecting the placement of thepattern such that a substantial portion of the defects on the specimendoes not overlap with the pattern. In some embodiments, determining theplacement of the pattern may include determining the placement of thecritical portions of the pattern with respect to locations of defects onthe specimen. For example, determining the placement of the pattern mayinclude selecting the placement of the pattern such that a substantialportion of defects on the specimen does not overlap with criticalportions of the pattern. In one particular example, inspection of ablank reticle substrate identifies a number of defects on the substrate.The design pattern to be printed on the reticle substrate may then bealigned and printed on the reticle substrate such that the defects onthe blank reticle substrate do not overlap any critical areas of thedesign pattern. In an additional embodiment, determining the placementof the pattern may include selecting the placement of the pattern suchthat an amount of overlap between defects on the specimen and criticalportions of the pattern is below a predetermined threshold. In thismanner, a certain degree of overlap between defects on the specimen andcritical areas on the specimen may be tolerated, and the design patternmay be printed such that the degree of overlap is below a certainthreshold.

In some embodiments, the method may also include determining overlapbetween defects on the specimen and critical portions of the pattern, asshown in step 124. In further embodiments, if the specimen is a blankreticle substrate, the method may include determining an amount ofoverlap between defects on the reticle and critical portions of thepattern. The degree of overlap between defects on the blank reticle andcritical areas of the design pattern may be an indicator of the expectednumber of critical defects that would be produced by using the patternedreticle to expose a wafer. Therefore, such an embodiment may alsoinclude estimating the number of critical defects that may be producedon a wafer using the reticle, as shown in step 126. In anotherembodiment, if the specimen is a blank reticle substrate, the method mayinclude determining alignment of the reticle with an exposure tooland/or wafer based on the placement of the pattern with respect to acoordinate system, as shown in step 128. For example, informationregarding the displacement of the design pattern with respect to nominalcoordinates may be stored and may be subsequently used to properly alignthe reticle with the stepper and/or the wafer. In a similar manners areticle may be selectively aligned with a wafer exhibiting defectsduring wafer patterning.

The computer-implemented method illustrated in FIG. 9 provides severaladvantages including, but not limited to, the ability to toleratedefects on blank reticle substrates and wafers, cost savings byreducing, and even eliminating, the need to replace or repair blankreticle substrates and wafers, and time savings by reducing, and eveneliminating, processing delays associated with rejection and replacementof the defective blank reticle substrates or wafers. The method shown inFIG. 9 may include any other steps of any other methods describedherein.

FIG. 10 is a flow chart illustrating an embodiment of acomputer-implemented method for determining the significance of adefect. Reticles are used as the master patterns in the manufacture ofsemiconductor devices. Automated inspections of reticles are standardsteps in the production of these semiconductor devices. The inspectionsare used to detect defects on the reticles, which may then be rejected,repaired, cleaned, or passed based on defect disposition criteria. Theinspections are critical because even one significant defect on areticle can cause every semiconductor device manufactured with thereticle to fail or be flawed in some way. As more complex semiconductordesigns are developed, the designs result in more complex reticles andmore complex lithographic techniques. Smaller design sizes combined withincreasing complexities have resulted in increasing difficulty indetecting and accurately dispositioning reticle defects. For example,there can be a substantially non-linear relationship between what is onthe reticle (design or defect) to what resulting pattern is generated onthe wafer.

Methods for determining the printability of a defect have beendeveloped. For example, a system and a method for determining reticledefect printability are illustrated in U.S. Pat. Nos. 6,076,465 to Vaccaet al. and 6,381,358 to Vacca et al. and U.S. patent application Ser.No. 10/074,857 entitled “System and Method for Determining ReticleDefect Printability” by Vacca et al., filed on Feb. 11, 2002, which areincorporated by reference as if fully set forth herein. Examples ofdesigner intent data and methods of use for reticle inspection areillustrated in U.S. Pat. No. 6,529,621 to Glasser et al. and PCTApplication No. WO 00/36525 by Glasser et al., which are incorporated byreference as if fully set forth herein.

The computer-implemented method described herein provides a method fordetermining the significance or potential significance of a defect on areticle. This method may utilize a reticle pattern generation system ora reticle inspection system. As shown in step 130, the method includesdetermining the design significance of different regions on a reticle.In some embodiments, the regions of greater or lesser designsignificance on a reticle may be determined by an automatic computerprogram with information about the reticle and the context of the fullreticle design. Determining the design significance of the differentregions on the reticle may or may not be performed during apre-processing step carried out before inspection. Alternatively,determining the design significance of the different regions may beperformed during inspection or during a post-processing step carried outafter inspection.

The method also includes determining the design significance of a defectdetected on the reticle, as shown in step 132. The design significanceis a measure of how the defect impacts the design of the reticle. Thedesign significance of the defect may be determined based on the designsignificance of the region on the reticle in which the defect islocated. Alternatively, the design significance of the defect may bedetermined by comparing data representative of the defect to a thresholdand determining that the defect has design significance if the data isgreater than the threshold. In some embodiments, the data representativeof the defect may include phase and/or transmittance of the defect, alateral dimension of the defect, or a distance between the defect andother features on the reticle. In one embodiment, the threshold may varydepending on the location of the defect on the reticle. Therefore, eachdefect or location on the reticle may have a threshold above which adefect may be determined to have design significance. For example, thethreshold may have a lower value in a region of the reticle having agreater design significance than the value of the threshold in a regionof the reticle having a lower design significance.

The method also includes determining the lithographic significance ofdifferent regions on the reticle, as shown in step 134. For example,information about the lithographic process in which this reticle will beused may be obtained. In one embodiment, the information about thelithographic process may be obtained from a fab database. In anotherembodiment, the information about the lithographic process may beobtained from simulation software that may be used to determine aprocess window for the lithographic process. In a different embodiment,the information about the lithographic process may be obtained fromexperimental results obtained using a process window characterization(PWC) reticle. Regions of greater or lesser lithographic criticality ona reticle may, in some embodiments, be determined by an automaticcomputer program with information about the design of the reticle andthe lithographic process. Determining the lithographic significance ofdifferent regions on the reticle may be performed during apre-processing step carried out before reticle inspection, duringreticle inspection, and/or during a post-processing step carried outafter reticle inspection.

The method further includes determining the lithographic significance ofa defect detected on the reticle, as shown in step 136. The lithographicsignificance is a measure of how the defect impacts a wafer patterned bya lithography process that uses the reticle. The lithographicsignificance of the defect may be determined based on the lithographicsignificance of the region on the reticle in which the defect islocated. Alternatively, the lithographic significance of the defect maybe determined by comparing data representative of the defect to athreshold and determining that the defect has lithographic significanceif the data is greater than the threshold. The data representative ofthe defect may include any of the data described above. In oneembodiment, the threshold may vary depending on the location of thedefect on the reticle. In this manner, each defect or location on thereticle may have a threshold above which a defect may be determined tohave lithographic significance. For example, the threshold may have alower value in a region of the reticle having a greater lithographicsignificance than the value of the threshold in a region of the reticlehaving a lower lithographic significance.

As shown in step 138, the method includes determining an overallsignificance of a defect detected on the reticle. The overallsignificance of the defect may be determined based on the designsignificance and the lithographic significance of the defect. Therefore,the method may be used to determine the overall significance of a defectby determining the design significance of the defect in a particularlocation on the reticle combined with the lithographic significance ofthe defect in a particular location on the wafer. The overallsignificance of the defect may be selected from one of the following 4categories: lithographically and design significant, lithographicallysignificant only, design significant only, and not significant. Eachdefect may be assigned to one of the 4 categories.

The chart shown in FIG. 11 is a conceptual diagram illustrating howdefects may fall into each of these categories. As shown in FIG. 11, thesignificance of defects may vary as a function of amplitude (ortransmittance) and phase as well as size. The significance of thedefects, however, may also vary as a function of other characteristicsof the defects and the reticle. For example, the significance of thedefects may vary as a function of the distance between the defects andother features on the reticle. As further shown in FIG. 11, differentdefects detected on a reticle may have design significance orlithographic significance. Of all of the defects that have some kind ofsignificance, an even smaller portion of these defects have both designand lithographic significance. Applying both criteria for significanceto defects allows the semiconductor manufacturing process to be analyzedor changed based on the most significant regions or defects on a reticlewhile retaining information (if desired) about the less significantregions or defects.

In some embodiments, the method may include determining processing ofthe reticle, as shown in step 140 of FIG. 10. In one such embodiment,the processing of the reticle may be determined based on the design,lithographic, and/or overall significance of individual defects on thereticle. Processing of the reticle may include, but is not limited to,rejecting the reticle, repairing the reticle, and/or cleaning thereticle. By combining the information about both types of significance,it may be possible to reduce or eliminate the necessity to reject,repair, or clean certain reticles.

In additional embodiments, the method may include determining one ormore parameters of a process used to repair a defect on the reticle, asshown in step 142. For example, one or more parameters of a process usedto repair a defect may be determined based on the design, lithographic,and/or overall significance of the defect. In this manner, one or moreof the parameters used to repair different defects on the reticle may bedifferent. For example, a defect that has a higher overall significancemay be repaired using a process that has a higher accuracy than theprocess that is used to repair a defect that has a lower overallsignificance. The repair process may include any of the repair processesdescribed herein and any other repair process known in the art.Determining processing of the reticle or one or more parameters of aprocess used to repair a defect on the reticle may be performed in anautomated manner thereby reducing, or even eliminating, the need for aperson to make the decision on dispositioning defects.

In one embodiment, the method may include generating a visualrepresentation of a defect detected on the reticle, as shown in step144. The visual representation may include one or more designationsassigned to the defect, which indicate the design, lithographic, and/oroverall significance of the defect. The visual representation may alsoinclude a two-dimensional visual representation of the defect, athree-dimensional visual representation of the defect, a two-dimensionalmap of a region on the reticle in which the defect is located, or atwo-dimensional map of the reticle on which the defect is located. Inaddition, the visual representation of the defect may be overlaid withother data representative of the defect, the region of the reticle inwhich the defect is located, or the reticle on which the defect islocated. For example, the visual representation of the defect mayinclude visual representations of other features on the reticle that maybe proximate to the defect and, in some cases, designations assigned tothe features, which may or may not indicate the design, lithographic,and/or overall significance of these features. In some embodiments, themethod may include generating a visual representation of individualregions on the reticle, as shown in step 146. In one such embodiment,the visual representation may include designations assigned to theindividual regions indicating the design, lithographic, and/or overallsignificance of the individual regions. This visual representation maybe further configured as described above. In this manner, the method maybe used to indicate regions or defects of greater or lesser significancewhen presenting results to a user. Furthermore, critical design regionsand/or critical lithographic regions may be indicated as well as regionsof high mask error enhancement factor (MEEF).

In an embodiment, the method may include determining an overallsignificance of different regions on the reticle, as shown in step 148.The overall significance of the different regions on the reticle may bedetermined based on the design significance and the lithographicsignificance of the different regions on the reticle. In someembodiments, the overall significance of the different regions on thereticle may be used to determine the overall significance of a defect onthe reticle. For example, a defect on the reticle may be assigned thesame overall significance as the region on the reticle in which thedefect is located. In such embodiments, the design significance and thelithographic significance of the defect may or may not be determined asdescribed above.

By combining the information about both types of significance, themethod can be used to improve the yield, cycle time, efficiency, andother aspects of the semiconductor manufacturing process concerningreticles. In particular, it may be possible to improve the patterngeneration process by adjusting system parameters based on thesignificance of a particular location on a reticle. In one embodiment,the method may include determining one or more parameters of a processused to fabricate the reticle, as shown in step 150. The parameters ofthe process may be determined based on the design, lithographic, and/oroverall significance of different regions of the reticle. In someembodiments, the parameters of the process may be determinedindependently for different regions on the reticle. In this manner, oneor more of the parameters of the process may be different for more thanone region on the reticle. As such, the parameters of the process mayvary independently across the reticle. For example, the parameters ofthe reticle fabrication process in a region of the reticle having ahigher overall significance than another region on the reticle may beselected such that the region having the higher overall significance isprocessed with greater writing fidelity than the other region. Rules forfabrication process tool parameters in regions of varying significancemay be manually set by a user or may be set automatically by a processorconfigured to perform the method shown in FIG. 10. Examples of reticlefabrication processes include pattern generation, etch, cleaning, andany other reticle fabrication process known in the art.

In a further embodiment, the method may include determining one or moreparameters of a process used to inspect the reticle, as shown in step152. The parameters that may be altered may be parameters of aninspection tool configured to perform reticle inspection. The parametersof the inspection process may be determined as described above. As such,the parameters of the inspection process may vary independently fromregion to region across the reticle. For example, the parameters of theinspection process may be selected to have higher sensitivity in oneregion than the sensitivity used to inspect other regions on thereticle. In particular, the defect sensitivity of reticle inspection maybe the greatest in the most lithographically and design significantregions of the reticle. The increased sensitivity in the mostlithographically and design significant regions of the reticle mayincrease the yield or performance of semiconductor devices fabricatedusing such a reticle. The inspection process for the reticle may be anysuitable inspection process known in the art such as inspection based onlight transmitted and/or reflected by the reticle and aerial imagingbased inspection.

For processing of data generated by reticle inspection, defect detectionin any of several modes (die:die detection, die:database inspection, orany other mode known in the art) may be performed. One or moreparameters of the inspection data processing may also be varied based onthe significance of a particular region or defect on the reticle. Theone or more parameters of data processing that may be altered include avalue of a threshold or an algorithm that is used for defect detection.In a similar manner, the parameters of a process used to review defectson the reticle may be determined as described above. Rules forinspection system and/or review system parameters in regions of varyingsignificance may be set manually by a user or may be set automaticallyby a processor configured to perform the method described herein.

In another embodiment, the method may include determining one or moreparameters of a process used to repair the reticle, as shown in step154. The parameters of the repair process may be determined as describedabove. As such, the parameters of the repair process may varyindependently from region to region across the reticle. For example, theparameters of the repair process may be selected to have higher accuracyin one region than the accuracy used to repair other regions on thereticle. Rules for repair tool parameters in regions of varyingsignificance may be set manually by a user or may be set automaticallyby a processor configured to perform the method described herein. Therepair process for the reticle may be any suitable repair process knownin the art such as chemically assisted laser removal, laser inducedshock wave removal, particle beam assisted repair, or cleaning thereticle using a wet or dry cleaning process such as etch or strippingprocesses, which are described in further detail above. The method shownin FIG. 10 may include any steps of any other methods described herein.

Program instructions implementing methods such as those described abovemay be transmitted over or stored on a carrier medium. The programinstructions may be executable on a computer system to perform any ofthe computer-implemented methods described herein. The carrier mediummay be a transmission medium such as a wire, cable, or wirelesstransmission link, or a signal traveling along such a wire, cable, orlink. The carrier medium may also be a storage medium such as aread-only memory, a random access memory, a magnetic or optical disk, ora magnetic tape. One or more data structures and/or rules databases maysimilarly be transmitted over or stored upon such a carrier medium.

A system configured to perform any of the computer-implemented methodsdescribed herein may include a processor. The processor may beconfigured to execute program instructions for performing one or more ofthe computer-implemented methods described herein. The processor may beany suitable processor known in the art. In one example, the processormay be an image computer. In another example, the processor may be anysuitable microprocessor known in the art.

The system and the processor may be configured in various ways. In oneembodiment, the system may be configured as a stand-alone system. Inthis manner, the system may not be coupled to another system or toolexcept by a transmission medium. For example, the processor of thesystem may be coupled to a processor of a reticle and/or waferinspection system by a transmission medium. One such configuration isshown in FIG. 2. The transmission medium may include any of thetransmission mediums described above. In one embodiment, the system maybe a stand-alone system that is coupled to an inspection system, adefect review system, a reticle fabrication tool, and/or a repair tool.In some embodiments, the system may be coupled to more than one systemand/or more than one tool. In another embodiment, the system may be astand-alone system that is coupled to a fab database. In an additionalembodiment the system may be coupled to a fab database in addition toanother system and/or tool.

In other embodiments, the processor of the system may be incorporatedinto an inspection system, a defect review system, a reticle fabricationtool, or a repair tool. For example, a processor of an inspection systemmay be configured to perform one or more of the computer-implementedmethods described above in addition to other standard functions of sucha processor. In the case of an inspection system, examples of suchstandard functions may include receiving and processing signalsgenerated by detectors of the inspection system and calibrating theinspection system.

In any of the above embodiments, the processor may be configured tocontrol one or more parameters of the inspection system, the defectreview system, the reticle fabrication tool, and/or the repair tool. Forexample, the processor may be configured to alter one or more parametersof the inspection system, the defect review system, the reticlefabrication tool, and/or the repair tool according to any of the aboveembodiments. In another embodiment, the processor may be configured tosend the altered parameters and instructions to change the parameters toa processor of an inspection system, a defect review system, a reticlefabrication tool, and/or a repair tool.

Further modifications and alternative embodiments of various aspects ofthe invention may be apparent to those skilled in the art in view ofthis description. For example, methods and systems for inspection ofwafers and reticles using designer intent data are provided.Accordingly, this description is to be construed as illustrative onlyand is for the purpose of teaching those skilled in the art the generalmanner of carrying out the invention. It is to be understood that theforms of the invention shown and described herein are to be taken as thepresently preferred embodiments. Elements and materials may besubstituted for those illustrated and described herein, parts andprocesses may be reversed, and certain features of the invention may beutilized independently, all as would be apparent to one skilled in theart after having the benefit of this description of the invention.Changes may be made in the elements described herein without departingfrom the spirit and scope of the invention as described in the followingclaims.

1.-85. (canceled)
 86. A method for monitoring fabrication of anintegrated circuit (IC) on a semiconductor wafer, comprising: generatinga product design profile (PDP) using an electronic design automation(EDA) tool, the PDP comprising an indication of a site in at least onelayer of the IC that is susceptible to a process fault; fabricating theat least one layer of the IC on the wafer; and applying a processmonitoring tool to perform a measurement at the site in the at least onelayer responsively to the PDP.
 87. The method according to claim 86,wherein applying the process monitoring tool comprises measuring adimension associated with one or more features of the IC at the site.88. The method according to claim 86, wherein generating the PDPcomprises making a determination that the site is critical to aperformance rating of the IC, and selecting the site responsively to thedetermination.
 89. The method according to claim 86, and comprisingpredicting a yield of the fabrication of the IC responsively to the PDPand to the measurement.
 90. A method for monitoring fabrication of anintegrated circuit (IC) on a semiconductor wafer, comprising: generatinga product design profile (PDP) using an electronic design automation(EDA) tool, the PDP comprising an identification of a region in at leastone layer of the IC that is characterized by a periodic pattern;fabricating the at least one layer of the IC on the wafer; and applyinga process monitoring tool to perform a measurement in the region of theat least one layer responsively to the periodic pattern.
 91. The methodaccording to claim 90, wherein generating the PDP comprises determiningan exact period of a repetitive feature in the periodic pattern, andwherein applying the process monitoring tool comprises capturingmultiple images of the feature at locations on the wafer that aremutually spaced by the exact period, and comparing each of the images toanother of the images or to a reference image.
 92. The method accordingto claim 90, wherein applying the process monitoring tool comprisesdetermining, responsively to the periodic pattern, a sensitivity settingto be applied by the process monitoring tool in detecting defects in theregion, wherein different sensitivity settings are applied by theprocess monitoring tool in different regions of the at least one layer.93. A method for monitoring fabrication of an integrated circuit (IC) ona semiconductor wafer, comprising: generating a product design profile(PDP) using an electronic design automation (EDA) tool, the PDPcomprising an identification of a plurality of regions in at least onelayer of the IC and a respective criticality parameter for each of theregions, indicative of a maximum tolerable defect size in each of theregions; fabricating at least one layer of the IC on the wafer; andapplying a process monitoring tool to perform a measurement in one ormore of the regions in at least one layer responsively to the respectivecriticality parameter.
 94. The method according to claim 93, whereinapplying the process monitoring tool comprises setting a defectdetection threshold in each of the one or more of the regionsresponsively to the respective criticality parameter.
 95. The methodaccording to claim 93, wherein applying the process monitoring toolcomprises selecting the one or more of the regions to inspectresponsively to the respective criticality parameter.
 96. The methodaccording to claim 93, wherein applying the process monitoring toolcomprises detecting a defect in one of the regions, and classifying thedefect responsively to the criticality parameter.
 97. A method formonitoring fabrication of an integrated circuit (IC) on a semiconductorwafer, comprising: designing a layout of at least one layer of the ICusing an electronic design automation (EDA) tool, at least one layercomprising a structure that is amenable to testing; generating a productdesign profile (PDP) using the EDA tool, the PDP comprising informationregarding the structure; fabricating at least one layer of the IC on thewafer; and applying a process monitoring tool to perform a measurementon the structure in at least one layer, responsively the information inthe PDP.